With the reduction in the sizes of semiconductor devices in recent years, the sizes of resist patterns used in lithography steps are also reduced. For this reason, even when a mask pattern is generated to be similar to a design layout pattern, and a resist pattern is formed by using the mask pattern, there may be a process conversion difference in the dimension of the processed pattern with respect to the dimension of the resist pattern. Therefore, in order to make the processed pattern more similar to the design layout pattern, it is desired to highly accurately correct the process conversion difference when the mask data are generated.